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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P0076
4-BIT SINGLE-CHIP MICROCONTROLLER
The PD75P0076 replaces the PD750068's internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the PD75P0076 supports programming by users, it is suitable for use in prototype testing for system development using the PD750064, 750066, and 750068 products, and for use in small-lot production. Detailed information about function is provided in the following user's manual. Be sure to read it before designing:
PD750068 User's Manual: U10670E
FEATURES
Compatible with PD750068 Memory capacity: * PROM : 16384 x 8 bits * RAM : 512 x 4 bits Can operate with same power supply voltage as the mask ROM version PD750068 VDD = 1.8 to 5.5 V On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V) 8-bit resolution x 8 channels Small shrink SOP package
ORDERING INFORMATION
Part Number Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD75P0076CU PD75P0076GT
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U10232EJ1V0DS00 (1st edition) Date Published December 1996 N Printed in Japan
The mark
shows major revised points.
(c)
1995
PD75P0076
Functional Outline
Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz with main system clock) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz with main system clock) * 122 s (@ 32.768 kHz with subsystem clock) 16384 x 8 bits 512 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 12 Connections of on-chip pull-up resistors can be specified by software: 7 Also used for analog input pins: 4 Connections of on-chip pull-up resistors can be specified by software: 12 Also used for analog input pins: 4 13-V withstand voltage
On-chip memory
PROM RAM
General-purpose register
Input/ output port
CMOS input
CMOS input/output
12
N-ch open-drain input/output pins Total Timer
8
32 4 * * * channels 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) 8-bit basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel
Serial interface
* 3-wire serial I/O mode *** MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode 8-bit resolution x 8 channels (1.8 V AVREF VDD) 16 bits * , 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock) * , 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock) * 2, 4, 32 kHz (@ 4.19 MHz with main system clock or @ 32.768 kHz with subsystem clock) * 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock) External: 3, Internal: 4 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode TA = -40 to +85 C VDD = 1.8 to 5.5 V * 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) * 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
A/D converter Bit sequential buffer Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts Test input System clock oscillator
Standby function Operating ambient temperature Power supply voltage Package
2
PD75P0076
CONTENTS
1. PIN CONFIGURATION (Top View) ................................................................................................... 2. BLOCK DIAGRAM ............................................................................................................................ 3. PIN FUNCTIONS ...............................................................................................................................
3.1 3.2 3.3 3.4 Port Pins ................................................................................................................................................... Non-port Pins ........................................................................................................................................... Equivalent Circuits for Pins ....................................................................................................................
4 5 6
6 7 9
Handling of Unused Pins ......................................................................................................................... 12
4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13
4.1 4.2 Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13 Setting of Stack Bank Selection (SBS) Register .................................................................................... 14
5. DIFFERENCES BETWEEN PD75P0076 AND PD750064, 750066 AND 750068 ........................ 15 6. MEMORY CONFIGURATION ............................................................................................................ 16 7. INSTRUCTION SET ........................................................................................................................... 18 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29
8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................. 29 Steps in Program Memory Write Operation ............................................................................................ 30 Steps in Program Memory Read Operation ............................................................................................ 31 One-time PROM Screening ..................................................................................................................... 32
9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33 10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49 11. PACKAGE DRAWINGS .................................................................................................................... 51 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53 APPENDIX A DIFFERENCES AMONG PD75068, 750068 AND 75P0076 ......................................... 54 APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55 APPENDIX C RELATED DOCUMENTS ................................................................................................. 58
3
PD75P0076
1. PIN CONFIGURATION (Top View)
* 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
PD75P0076CU
* 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD75P0076GT
XT1 XT2 RESET X1 X2 P33/MD3 P32/MD2 P31/MD1 P30/MD0 AVSS P63/KR3/AN7 P62/KR2/AN6 P61/KR1/AN5 P60/KR0/AN4 P113/AN3 P112/AN2 P111/AN1 P110/AN0 AVREF VPP VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40/D0 P41/D1 P42/D2 P43/D3 P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ
In normal operation mode, make sure to connect VPP directly to VDD.
Pin Identification
AN0 to AN7 AVREF AVSS BUZ D0 to D7 INT0, INT1, INT4 INT2 KR0 to KR3 MD0 to MD3 P00 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 : : : : : : : : : : : : : : : : Analog Input 0 to 7 Analog Reference Analog Ground Buzzer Clock Data Bus 0 to 7 External Vectored Interrupt 0, 1, 4 External Test Input 2 Key Return Mode Selection 0 to 3 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P110 to P113 PCL PTO0, PTO1 RESET SB0, SB1 SCK SI SO TI0, TI1 VDD VPP VSS X1, X2 XT1, XT2 : : : : : : : : : : : : : : Port 11 Programmable Clock Programmable Timer Output 0, 1 Reset Input Serial Data Bus 0, 1 Serial Clock Serial Input Serial Output Timer Input 0, 1 Positive Power Supply Programmable Power Supply Ground Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2
4
PD75P0076
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER/WATCHDOG TIMER INTBT BUZ/P23 WATCH TIMER INTW INTW INTT0
PROGRAM COUNTER
PORT0
4
P00 to P03
SP (8) ALU CY
PORT1
4
P10 to P13
PORT2
4
P20 to P23 P30/MD0 to P33/MD3 P40/D0 to P43/D3 P50/D4 to P53/D7 P60 to P63
PORT3 SBS BANK PORT4
4
TI0/P13 PTO0/P20
8-BIT TIMER/ EVENT CASCADED COUNTER#0 16-BIT
TIMER/ EVENT 8-BIT COUNTER TIMER/ EVENT COUNTER#1
4
TI1/P12/INT2 PTO1/P21
GENERAL REG.
PORT5
4
INTT1 SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCSI TOUT0 INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1 KR0/P60 to 4 KR3/P63 AN0/P110 to AN3/P113 AN4/P60 to AN7/P63 AVREF AVSS INTERRUPT CONTROL CLOCKED SERIAL INTERFACE
PROGRAM MEMORY (PROM) 16384 x 8 BITS
PORT6 DATA MEMORY (RAM) 512 x 4BITS
4
PORT11
4
P110 to P113
DECODE AND CONTROL
BIT SEQ. BUFFER (16)
fx/2N
CPU CLOCK
4 4
SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT CONTROL CONTROL DIVIDER SUB MAIN A/D CONVERTER PCL/P22 XT1 XT2 X1 X2 VPP VDD VSS RESET
5
PD75P0076
3. PIN FUNCTIONS
3.1 Port Pins
8-bit accessible Not available After reset Input I/O circuit typeNote 1 -A -B -C This is a 4-bit input port (PORT1). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. P10/INT0 can select a noise elimination circuit. Not available Input -C
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40
Note 2
I/O I I/O I/O I/O I
Alternate function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/INT2 TI0
Function This is a 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistors are software-specifiable in 3-bit units.
I/O
PTO0 PTO1 PCL BUZ
This is a 4-bit I/O port (PORT2). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units.
Not available
Input
E-B
I/O
MD0 MD1 MD2 MD3
This is a programmable 4-bit I/O port (PORT3). Input and output can be specified in single-bit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units.
Not available
Input
E-B
I/O
D0 D1 D2 D3
P41Note 2 P42Note 2 P43Note 2 P50
Note 2
This is an N-ch open-drain 4-bit I/O port (PORT4). In the open-drain mode, withstands up to 13 V. Also used as data I/O pin (lower 4 bits) for program memory (PROM) write/verify.
Available
High impedance
M-E
I/O
D4 D5 D6 D7
P51Note 2 P52Note 2 P53Note 2 P60 P61 P62 P63 P110 P111 P112 P113 I I/O
This is an N-ch open-drain 4-bit I/O port (PORT5). In the open-drain mode, withstands up to 13 V. Also used as data I/O pin (upper 4 bits) for program memory (PROM) write/verify.
High impedance
M-E
KR0/AN4 KR1/AN5 KR2/AN6 KR3/AN7 AN0 AN1 AN2 AN3
This is a programmable 4-bit I/O port (PORT6). Input and output can be specified in single-bit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units.
Not available
Input
-D
This is a 4-bit input port (PORT11).
Not available
Input
Y-A
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs. 2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
6
PD75P0076
3.2 Non-port Pins (1/2)
After reset Input Circuit typeNote -C
Pin name TI0 TI1 PTO0 PTO1 PCL BUZ
I/O I
Alternate function P13 P12/INT2
Function Inputs external event pulses to the timer/event counter. Timer/event counter output
O
P20 P21 P22 P23
Input
E-B
Clock output Optional frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select a noise eliminator. Rising edge detection testable input Noise eliminator/ asynchronous selection Asynchronous Input Input -A -B
SCK SO/SB0
I/O
P01 P02
SI/SB1
P03
-C
INT4
I
P00

INT0 INT1
I
P10 P11
-C
INT2
P12/TI1
Asynchronous
KR0 to KR3
I
P60/AN4 to P63/AN7 P110 to P113 P60/KR0 to P63/KR3
Falling edge detection testable input
Input
-D
AN0 to AN3 AN4 to AN7
I
Analog signal input
Input
Y-A -D
AVREF AVSS X1 X2
-- -- I --
-- -- --
A/D converter reference voltage A/D converter reference GND potential Crystal/ceramic connection pin for the main system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2.
-- -- --
Z-N Z-N --
XT1 XT2
I --
--
Crystal connection pin for the subsystem clock oscillator. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin.
--
--
RESET
I
--
System reset input (low-level active)
--

Note Circuit types enclosed in brackets indicate Schmitt triggered inputs.
7
PD75P0076
3.2 Non-port Pins (2/2)
After reset Input Circuit type E-B
Pin name MD0 to MD3
I/O I
Alternate function P30 to 33
Function Mode selection for program memory (PROM) write/verify. Data bus pin for program memory (PROM) write/verify.
D0 to D3 D4 to D7 VPPNote
I/O
P40 to 43 P50 to 53
Input
M-E
--
--
Programmable voltage supply in program memory (PROM) write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode. Positive power supply Ground
--
--
VDD VSS
-- --
-- --
-- --
-- --
Note During normal operation, the VPP pin will not operate normally unless connected to VDD pin.
8
PD75P0076
3.3 Equivalent Circuits for Pins The equivalent circuits for the PD75P0076's pin are shown in schematic diagrams below.
(1/3) TYPE A TYPE D VDD VDD Data P-ch IN Output disable N-ch P-ch OUT
N-ch
CMOS standard input buffer TYPE B
Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch
IN
Data Type D Output disable
IN/OUT
Schmitt trigger input with hysteresis characteristics.
Type A
P.U.R. : Pull-Up Resistor
TYPE B-C VDD P.U.R. P.U.R. enable
TYPE F-A VDD P.U.R. P.U.R. enable Data IN Type D Output disable P-ch
P-ch
IN/OUT
P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics.
Type B
P.U.R. : Pull-Up Resistor
9
PD75P0076
(2/3) TYPE F-B TYPE Y
VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) VDD P-ch IN/OUT AVSS N-ch Input enable P-ch IN VDD Sampling C AVSS Reference voltage (from the voltage tap of the serial resistor string) P-ch N-ch + - VDD
P.U.R. : Pull-Up Resistor
TYPE M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT
TYPE Y-A
IN instruction
Type A Data Output disable N-ch IN Type Y Input butfer
P.U.R. : Pull-Up Resistor
TYPE M-E* IN/OUT Data Output disable VDD Input instruction P-ch P.U.R. Note Voltage control circuit N-ch (+13 V withstand voltage)
(+13 V withstand voltage)
Note This is a pull-up resistor which only operates when an input instruction is executed (when the pin is low a current flows from VDD to the pin).
10
PD75P0076
(3/3) TYPE Y-D VDD AVREF P.U.R. P.U.R. enable P-ch TYPE Z-N
Data Output disable Type D
IN/OUT Reference voltage
Type B
ADEN Type Y P.U.R.: Pull-Up Resistor
N-ch
AVSS
11
PD75P0076
3.4 Handling of Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30/MD0 to P33/MD3 P40/D0 to P43/D3 P50/D4 to P53/D7 P60/KR0/AN4 to P63/KR3/AN7 Input mode : independently connected to VSS or VDD through resistor Output mode : open P110/AN0 to P113/AN3 XT1 XT2 VPP AVREF AVSS
Note Note
Recommended connection Connect to VSS or VDD Independently connect to VSS or VDD through resistor Connected to VSS Connect to VSS or VDD
Input mode
: independently connected to VSS or VDD through resistor
Output mode : open
Connected to VSS
Connected to VSS or VDD Connect to VSS or VDD Open Make sure to connect directly to VDD Connect to VSS
Note When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).
12
PD75P0076
4. SWITCHING BETWEEN Mk I AND Mk II MODES
Setting a stack bank selection (SBS) register for the PD75P0076 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the PD750064, 750066, and 750068 using the PD75P0076. When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of PD750064, 750066, and 750068) When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of PD750064, 750066, and 750068)
4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the PD75P0076. Table 4-1. Differences between Mk I Mode and Mk II Mode
Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank Stack bytes Instruction Instruction BRA !addr1 CALLA !addr1 CALL !addr PC13 to 0 16384 512 x 4 Selectable from memory banks 0 and 1 2 bytes Not provided 3 machine cycles 2 machine cycles Mk I mode of PD750064, 750066, and 750068 3 bytes Provided 4 machine cycles 3 machine cycles Mk II mode of PD750064, 750066, and 750068 Mk I Mode Mk II Mode
execution time CALLF !faddr Supported mask ROM versions and mode
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode.
13
PD75P0076
4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 100xBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 000xBNote. Note Set the desired value for x. Figure 4-1. Format of Stack Bank Selection Register
Address F84H
3
2
1
0
Symbol SBS
SBS3 SBS2 SBS1 SBS0
Stack area specification
0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Setting prohibited
0
Be sure to enter "0" for bit 2.
Mode selection specification
0 1 Mk II mode Mk I mode
Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to "0" to enter the Mk II mode before using the instructions. 2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register.
14
PD75P0076
5. DIFFERENCES BETWEEN PD75P0076 AND PD750064, 750066 AND 750068
The PD75P0076 replaces the internal mask ROM in the PD750064, 750066, and 750068 with a one-time PROM and features expanded ROM capacity. The PD75P0076's Mk I mode supports the Mk I mode in the PD750064, 750066, and 750068 and the PD75P0076's Mk II mode supports the Mk II mode in the PD750064, 750066, and 750068. Table 5-1 lists differences among the PD75P0076 and the PD750064, 750066, 750068. Be sure to check the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. For further description of CPU functions and internal hardware, see the PD750064 and 750068 Preliminary Product Information (U10165E).
Table 5-1. Differences between PD75P0076 and PD750064, 750066, 750068
Item Program counter Program memory (bytes) Data memory (x 4 bits) Mask options Pull-up resistor for ports 4 and 5 Wait time when RESET Feedback resistor of subsystem clock Pin configuration Pins 6 to 9 Pin 20 Pins 34 to 37 Pins 38 to 41 Other
PD750064
12-bit Mask ROM 4096 512
PD750066
PD750068
13-bit 14-bit
PD75P0076
Mask ROM 6144
Mask ROM 8192
One-time PROM 16384
Yes (on-chip specifiable) Yes (217/fX, 215/fX selectable)Note Yes (Use/not use selectable) P33 to P30 IC P53 to P50 P43 to P40
No (off chip) No (fixed at 215/fX)Note No (Use) P33/MD3 to P30/MD0 VPP P53/D7 to P53/D4 P43/D3 to P40/D0
Noise resistance and noise radiation may differ due to different circuit complexities and mask layouts.
Note 217/fX is 21.8 ms in 6.0 MHz operation and 31.3 ms in 4.19 MHz operation. 215/fX is 5.46 ms in 6.0 MHz operation and 7.81 ms in 4.19 MHz operation. Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
15
PD75P0076
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
7 0000H MBE 6 RBE 0 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE RBE INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1 start address (upper 6 bits) INTT1 start address (lower 8 bits) Branch address for the following instructions * BR BCDE * BR BCXA * BR !addr * BRA !addr1 Note * CALLA !addr1 Note BRCB !caddr instruction branch address CALLF !faddr instruction entry address
0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
CALL !addr instruction subroutine entry address BR $addr instruction relative branch address (-15 to -1, +2 to +16)
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Branch destination address specified by GETI instruction, subroutine entry address
Note Can be used only in Mk II mode. Remark For instructions other than those noted above, the "BR PCDE" and "BR PCXA" instructions can be used to branch to addresses with changes in the PC's lower 8 bits only.
16
PD75P0076
Figure 6-2. Data Memory Map
Data memory General register area 000H (32 x 4) 01FH 020H
Memory bank
Stack area
Note
0 256 x 4 (224 x 4)
Data area static RAM (512 x 4)
0FFH 100H
256 x 4
1
1FFH
Unimplemented
F80H
Peripheral hardware area FFFH
128 x 4
15
Note Either memory bank 0 or 1 can be selected as the stack area.
17
PD75P0076
7. INSTRUCTION SET
(1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, see the RA75X Assembler Package User's Manual-Language (EEU1363)). When there are several codes, select and use just one. Uppercase letters, and + and - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description, see the PD750068 User's Manual (U10670E)). Labels that can be entered for fmem and pmem are restricted.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 3FFFH immediate data or label 000H to 3FFFH immediate data or label (in Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT0 to PORT6, PORT11 IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW RB0 to RB3 MB0, MB1, MB15 Coding format
Note When processing 8-bit data, only even addresses can be specified.
18
PD75P0076
(2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority select register : Interrupt enable flag : Register bank select register : Memory bank select register : Processor clock control register : Delimiter for address and bit : Contents of address xx : Hexadecimal data
PORTn : Port n (n = 0 to 6, 11)
19
PD75P0076
(3) Description of symbols used in addressing area
*1 MB = MBE * MBS MBS = 0, 1, 15 *2 *3 MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS MBS = 0, 1, 15 *4 *5 *6 *7 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 (Current PC) +2 to (Current PC) +16 *8 caddr = 0000H to 0FFFH (PC13, 12 = 00B) or 1000H to 1FFFH (PC13, 12 = 01B) or 2000H to 2FFFH (PC13, 12 = 10B) or 3000H to 3FFFH (PC13, 12 = 11B) *9 *10 *11 faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 0000H to 3FFFH (Mk II mode only) Program memory addressing Data memory addressing
Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas.
20
PD75P0076
(4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip .......................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction ......... S = 1 * Skipped instruction is 3-byte instructionNote ................... S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times.
21
PD75P0076
Group Transfer
Mnemonic MOV
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA
No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL)
Operation
Addressing area
Skip condition String-effect A
String-effect A String-effect B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
2 + S A (HL), then L L + 1 2 + S A (HL), then L L - 1 1 2 1 2 2 2 2 2 2 2 2 2 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp' reg1 A rp'1 XA A (HL)
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
2 + S A (HL), then L L + 1 2 + S A (HL), then L L - 1 1 2 2 2 1 2 3 3 3 3 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM XA (BCDE)ROMNote XA (BCXA)ROM
Note
Table reference
MOVT
XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA
*11 *11
Note As for the B register, only the lower 2 bits are valid.
22
PD75P0076
Group Bit transfer
Mnemonic MOV1
Operand CY, fmem.bit CY, pmem.@L CY, @H + mem.bit fmem.bit, CY pmem.@L, CY @H + mem.bit, CY
No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2
Operation CY (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0.bit) (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0.bit) CY
Addressing area *4 *5 *1 *4 *5 *1
Skip condition
Operation
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
1 + S A A + n4 2 + S XA XA + n8 1 + S A A + (HL) 2 + S XA XA + rp' 2 + S rp'1 rp'1 + XA 1 2 2 A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY *1 *1 *1
carry carry carry carry carry
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
1 + S A A - (HL) 2 + S XA XA - rp' 2 + S rp'1 rp'1 - XA 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A^n4 A A^(HL) XA XA^rp' rp'1 rp'1^XA A Avn4 A Av(HL) XA XAvrp' rp'1 rp'1vXA A Avn4 A Av(HL) XA XAvrp' rp'1 rp'1vXA
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
AND
A, #n4 A, @HL XA, rp' rp'1, XA
*1
OR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
23
PD75P0076
Group Accumulator manipulate Increment/ decrement
Mnemonic RORC NOT INCS A A reg rp1
Operand
No. of Machine bytes cycle 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2
Operation CY A0, A3 CY, An-1 An AA
Addressing area
Skip condition
1 + S reg reg + 1 1 + S rp1 rp1 + 1 2 + S (HL) (HL) + 1 2 + S (mem) (mem) + 1 1 + S reg reg - 1 2 + S rp' rp' - 1 2 + S Skip if reg = n4 2 + S Skip if (HL) = n4 1 + S Skip if A = (HL) 2 + S Skip if XA = (HL) 2 + S Skip if A = reg 2 + S Skip if XA = rp' 1 1 CY 1 CY 0 *1 *1 *1 *1 *3
reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
@HL mem DECS reg rp' Compare SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulate SET1 CLR1 SKT NOT1 CY CY CY CY
1 + S Skip if CY = 1 1 CY CY
CY = 1
24
PD75P0076
Group Memory bit manipulate
Mnemonic SET1
Operand mem.bit fmem.bit pmem.@L @H + mem.bit
No. of Machine bytes cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1
Operation
Addressing area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip condition
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit(L1-0)) 0 (H + mem3-0.bit) 0
CLR1
mem.bit fmem.bit pmem.@L @H + mem.bit
SKT
mem.bit fmem.bit pmem.@L @H + mem.bit
2 + S Skip if(mem.bit) = 1 2 + S Skip if(fmem.bit) = 1 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 2 + S Skip if(H + mem3-0.bit) = 1 2 + S Skip if(mem.bit) = 0 2 + S Skip if(fmem.bit) = 0 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 2 + S Skip if(H + mem3-0.bit) = 0 2 + S Skip if(fmem.bit) = 1 and clear 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 and clear 2 + S Skip if(H + mem3-0.bit) = 1 and clear 2 2 2 2 2 2 2 2 2 CY CY^(fmem.bit) CY CY^(pmem7-2 + L3-2.bit(L1-0)) CY CY^(H + mem3-0.bit) CY CYv(fmem.bit) CY CYv(pmem7-2 + L3-2.bit(L1-0)) CY CYv(H + mem3-0.bit) CY CYv(fmem.bit) CY CYv(pmem7-2 + L3-2.bit(L1-0)) CY CYv(H + mem3-0.bit)
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
SKF
mem.bit fmem.bit pmem.@L @H + mem.bit
SKTCLR
fmem.bit pmem.@L @H + mem.bit
AND1
CY, fmem.bit CY, pmem.@L
CY, @H + mem.bit 2 OR1 CY, fmem.bit CY, pmem.@L 2 2
CY, @H + mem.bit 2 XOR1 CY, fmem.bit CY, pmem.@L 2 2
CY, @H + mem.bit 2
25
PD75P0076
Group Branch
Mnemonic BRNote 1
Operand addr
No. of Machine bytes cycle -- --
Operation PC13-0 addr Assembler selects the most appropriate instruction among the following: * BR !addr * BRCB !caddr * BR $addr PC13-0 addr1 Assembler selects the most appropriate instruction among the following: * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC13-0 addr PC13-0 addr PC13-0 addr1 PC13-0 PC13-8 + DE PC13-0 PC13-8 + XA PC13-0 BCDENote 2 PC13-0 BCXA PC13-0 addr1 PC13-0 PC13, 12 + caddr11-0
Note 2
Addressing area *6
Skip condition
addr1
--
--
*11
!addr $addr $addr1 PCDE PCXA BCDE BCXA BRA
Note 1
3 1 1 2 2 2 2 3 2
3 2 2 3 3 3 3 3 2
*6 *7
*6 *6 *11 *8
!addr1 !caddr
BRCB
Notes 1. Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 2. As for the B register, only the lower 2 bits are valid.
26
PD75P0076
Group Subroutine stack control
Mnemonic CALLANote
Operand !addr1
No. of Machine bytes cycle 3 3
Operation (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 5) 0, 0, PC13,12 (SP - 2) X, X, MBE, RBE PC13-0 addr1, SP SP - 6
Addressing area *11
Skip condition
CALL
Note
!addr
3
3
(SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, 12 PC13-0 addr, SP SP - 4
*6
4
(SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 5) 0, 0, PC13, 12 (SP - 2) X, X, MBE, RBE PC13-0 addr, SP SP - 6
CALLFNote
!faddr
2
2
(SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, 12 PC13-0 000 + faddr, SP SP - 4
*9
3
(SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 5) 0, 0, PC13, 12 (SP - 2) X, X, MBE, RBE PC13-0 000 + faddr, SP SP - 6
RET
Note
1
3
MBE, RBE, PC13, 12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 X, X, MBE, RBE (SP + 4) PC11-0 (SP)(SP + 3)(SP + 2) 0, 0, PC13, 12 (SP + 1) SP SP + 6
RETS
Note
1
3 + S MBE, RBE, PC13, 12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 then skip unconditionally X, X, MBE, RBE (SP + 4) PC11-0 (SP)(SP + 3)(SP + 2) 0, 0, PC13, 12 (SP + 1) SP SP + 6 then skip unconditionally
Unconditional
RETI
1
3
MBE, RBE, PC13, 12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 0, 0, PC13, 12 SP + 1 PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6
Note Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
27
PD75P0076
Group Subroutine stack control
Mnemonic PUSH rp BS POP rp BS
Operand
No. of Machine bytes cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Operation (SP - 1)(SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1)(SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME(IPS.3) 1 IEXXX 1 IME(IPS.3) 0 IEXXX 0 A PORTn (n = 0 to 6, 11)
Addressing area
Skip condition
Interrupt control
EI IEXXX DI IEXXX
2 2 2 2 2 2 2 2 2 1
I/O
IN
Note 1
A, PORTn XA, PORTn
XA PORTn + 1, PORTn (n = 4) PORTn A (n = 2 to 6)
OUTNote 1
PORTn, A PORTn, XA
PORTn + 1, PORTn XA (n = 4) Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n (n = 0 to 3) MBS n (n = 0, 1, 15) * When using TBR instruction
-------------------------
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2 1
GETI
Note 2, 3
taddr
*10
-----------
PC13-0 (taddr)5-0 + (taddr + 1)
* When using TCALL instruction (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, 12 PC13-0 (taddr)5-0 + (taddr + 1)
-------------------------
SP SP - 4
-----------
* When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions 1 3 * When using TBR instruction PC13-0 (taddr)5-0 + (taddr + 1)
------------------------------
Determined by referenced instruction *10
-----------
4
* When using TCALL instruction (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 5) 0, 0, PC13, 12 (SP - 2) X, X, MBE, RBE PC13-0 (taddr)5-0 + (taddr + 1)
------------------------------
SP SP - 6
-----------
3
* When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions
Determined by referenced instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction's table definitions. 3. Double box indicates support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
28
PD75P0076
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory in the PD75P0076 is a 16384 x 8-bit electronic write-enabled one-time PROM. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1 pins is used instead of address input as a method for updating addresses.
Pin name VPP X1, X2 MD0 to MD3 D0/P40 to D3/P43 (lower 4) D4/P50 to D7/P53 (upper 4) VDD Function Pin (usually VDD) where programming voltage is applied during program memory write/verify Clock input pin for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify 8-bit data I/O pin for program memory write/verify Pin where power supply voltage is applied. Power voltage range for normal operation is 1.8 to 5.5 V. Apply 6 V for program memory write/verify.
Caution Pins not used for program memory write/verify should be handled as follows. * All unused pins except XT2 ...... Connect to Vss via a pull-down resistor * XT2 pin ........................................ Leave open
8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the PD75P0076's VDD pin and +12.5 V is applied to its VPP pin, program memory write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation mode
X: L or H
29
PD75P0076
8.2 Steps in Program Memory Write Operation High-speed program memory write can be executed via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V to VPP. (6) Write data using 1-ms write mode. (7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) to (7). (8) X [= number of write operations from steps (6) to (7)] x 1 ms additional write (9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address. (10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the VDD and VPP pins. (13) Power supply OFF The following diagram illustrates steps (2) to (9).
X repetitions Write Verify Additional write Address increment
VPP VPP VDD
VDD + 1 VDD VDD
X1
D0/P40-D3/P43 D4/P50-D7/P53
Data input
Data output
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
30
PD75P0076
8.3 Steps in Program Memory Read Operation The PD75P0076 can read out the program memory contents via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V to VPP. (6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) Zero-clear mode for program memory addresses. (8) Apply +5 V to the VDD and VPP pins. (9) Power supply OFF The following diagram illustrates steps (2) to (7).
VPP VPP VDD
VDD + 1 VDD VDD
X1
D0/P40-D3/P43 D4/P50-D7/P53
Data output
Data output
MD0/P30
MD1/P31
"L"
MD2/P32
MD3/P33
31
PD75P0076
8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the hightemperature conditions shown below, the PROM should be verified.
Storage temperature 125 C Storage time 24 hours
32
PD75P0076
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Power supply voltage PROM power supply voltage Input voltage VI1 VI2 Output voltage Output current high VO IOH Per pin Total of all pins Output current low IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Except ports 4, 5 Ports 4, 5 (N-ch open drain) -0.3 to VDD +0.3 -0.3 to +14 -0.3 to VDD +0.3 -10 -30 30 220 -40 to +85 V V V mA mA mA mA C Symbol VDD VPP Test Conditions Rating -0.3 to +7.0 -0.3 to +13.5 Unit V V
Tstg
-65 to +150
C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. CAPACITANCE (TA = 25C,VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
33
PD75P0076
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator
C1 C2
Recommended constant
X1 X2
Parameter Oscillation frequency (fx) Oscillation stabilization timeNote 3
Note 1
Test conditions
MIN. 1.0
TYP.
MAX. 6.0Note 2
Unit MHz
After VDD reaches oscillation voltage range MIN. 1.0
Note 1
4
ms
Crystal resonator
C1
X1
X2
Oscillation frequency (fx)
C2
6.0Note 2
MHz
Oscillation stabilization timeNote 3
VDD = 4.5 to 5.5 V
10 30 1.0 6.0Note 2
ms
External clock
X1 X2
X1 input frequency (fx)
Note 1
MHz
X1 input high-/low-level width (tXH, tXL)
83.3
500
ns
Notes 1. The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. When the power supply voltage is 1.8 V VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fx 6.0 MHz, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required 0.95 s. Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
34
PD75P0076
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator
C3
Recommended constant
XT1 XT2 R C4
Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote 2
Note 1
Test conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
VDD = 4.5 to 5.5 V
1.0
2 10
s
External clock
XT1 XT2
XT1 input frequency (fXT)
Note 1
32
100
kHz
XT1 input high-/low-level width (tXTH, tXTL)
5
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD. Caution When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillation circuit. Special care should therefore be taken for wiring method when the subsystem clock is used.
35
PD75P0076
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS CERAMIC RESONATOR (TA = -20 to +80 C)
Oscillation Circuit Constants (pF) C1 100 100 -- 4.0 30 -- 4.19 30 -- 6.0 30 -- 30 -- C2 100 100 -- 30 -- 30 -- 30 -- 30 -- 1.8 2.6 1.8 Oscillation Voltage Range (VDD) MIN. 2.2 2.0 MAX. 5.5 Rd = 5.6 K -- With on-chip capacitor -- With on-chip capacitor -- With on-chip capacitor -- With on-chip capacitor -- With on-chip capacitor
Manufacturer Murata Mfg. Co., Ltd.
Product Name CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA4.19MG CST4.19MGW CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU
Frequency (MHz) 1.0 2.0
Remarks
Note When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used as a ceramic resonator, a limiting resistor (Rd = 5.6 k) is required (see the figure below). Other recommended resonators do not require such a limiting resistor.
X1 CSB1000J C1
X2 Rd C2
Caution The oscillation circuit constants and oscillation voltage range only indicate the conditions under which the circuit can oscillate stably, and do not guarantee the oscillation frequency accuracy. If oscillation frequency accuracy is required in the actual circuit, it is necessary to adjust oscillation frequencies in the actual circuit, and you should consult directly with the manufacturer of the resonator used.
36
PD75P0076
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current low Symbol IOL Per pin Total of all pins Input voltage high VIH1 Ports 2, 3, and 11 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH3 Ports 4, 5 (N-ch open-drain) VIH4 Input voltage low VIL1 X1, XT1 Ports 2-5, 11 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL3 Output voltage high Output voltage low VOH VOL1 X1, XT1 SCK, SO, Ports 2, 3, 6 SCK, SO, Ports 2-6 IOH = -1.0 mA IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 When N-ch open-drain pull-up resistor 1 k Pins other than X1, XT1 X1, XT1 VIN = 13 V VIN = 0 V Ports 4, 5 (N-ch open-drain) Ports 4, 5, pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open-drain) When input instruction is not executed ILIL3 Ports 4, 5 (N-ch opendrain) When input instruction is executed Output leakage current high Output leakage current low On-chip pull-up resistor ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 13 V VOUT = 0 V VDD = 5.0 V VDD = 3.0 V -10 -3 0.4 0.2VDD V V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 0.2 2.0 Test conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V
Input leakage current high
ILIH1 ILIH2 ILIH3
VIN = VDD
3 20 20 -3 -20 -3
A A A A A A A A A A A A
Input leakage current low
ILIL1 ILIL2
-30 -27 -8 3 20 -3
SCK, SO/SB0, SB1, Ports 2, 3, 6 Ports 4, 5 (N-ch open-drain)
RL
VIN = 0 V
Ports 0-3, 6 (Excluding P00 pin)
50
100
200
k
37
PD75P0076
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Supply current Note 1 Symbol IDD1 6.0 MHzNote 2 Crystal oscillation IDD2 C1 = C2 = 22 pF Test conditions VDD = 5.0 V 10%Note 3 VDD = 3.0 V 10% HALT mode
Note 4
MIN.
TYP. 3.4 0.8 0.9 0.5 2.7 0.6 0.8 0.4 42 23 42 40 40 8 4 8 7 7
MAX. 10.2 2.4 2.7 1.5 7.4 1.8 2.4 1.2 126 69 84 120 80 24 12 16 21 14
Unit mA mA mA mA mA mA mA mA
VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD1
4.19 MHzNote 2 Crystal oscillation
VDD = 5.0 V 10%Note 3 VDD = 3.0 V 10% HALT mode
Note 4
IDD2
C1 = C2 = 22 pF
VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD3
32.768 kHz
Note 5
Low-voltage mode
Note 6
VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C
A A A A A A A A A A
Crystal oscillation
Low current consumption mode IDD4 HALT mode
Note 7
VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C Lowvoltage VDD = 3.0 V 10% VDD = 2.0 V 10%
modeNote 6 VDD = 3.0 V, TA = 25C Low current VDD = 3.0 V 10% consumption VDD = 3.0 V, modeNote 7 TA = 25C IDD5 XT1 = 0 V STOP mode
Note 8
VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C
0.05 0.02 0.02
10 5.0 3.0
A A A
Notes 1. Not including currents flowing in on-chip pull-up resistors. 2. Including oscillation of the subsystem clock. 3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed mode. 4. When PCC is set to 0000 and the device is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 6. When the sub-oscillation circuit control register (SOS) is set to 0000. 7. When SOS is set to 0010. 8. When SOS is set to 00x1, the feedback resistors of the sub-oscillation circuit is cutoff. (x: don't care)
38
PD75P0076
AC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle time
Note 1
Symbol tCY Operating on main system clock Operating on subsystem clock fTI VDD = 2.7 to 5.5 V
Test conditions VDD = 2.7 to 5.5 V
MIN. 0.67 0.95 114
TYP.
MAX. 64 64
Unit
s s s
(Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency TI0, TI1 input high-/low-level width Interrupt input high-/ low-level width tTIH, tTIL
122
125
0 0
1.0 275
MHz kHz
VDD = 2.7 to 5.5 V
0.48 1.8
s s s s s s s
tINTH, tINTL INT0
IM02 = 0 IM02 = 1
Note 2 10 10 10 10
INT1, 2, 4 KR0 to KR3 RESET low-level width tRSL
Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC) and the
Cycle Time tCY [ s] 6 5 4 3 64 60
tCY vs VDD (At main system clock operation)
processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fx is set by setting the interrupt mode register (IM0).
Guaranteed Operation Range
2
1
0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V]
39
PD75P0076
SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high-/low-level width SI Note 1 setup time (to SCK) SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL1, tKH1
VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150
tSIK1
VDD = 2.7 to 5.5 V
150 500
hold time
tKSI1
VDD = 2.7 to 5.5 V
400 600
(from SCK) SCKSONote 1 output delay time tKSO1 RL = 1 k, CL = 100 pFNote 2 VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high-/low-level width SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL2, tKH2
VDD = 2.7 to 5.5 V
400 1600
setup time
tSIK2
VDD = 2.7 to 5.5 V
100 150
(to SCK) SI Note 1 hold time (from SCK) SCKSONote 1 output delay time tKSO2 RL = 1 k, CL = 100 pFNote 2 VDD = 2.7 to 5.5 V tKSI2 VDD = 2.7 to 5.5 V
400 600 0 0 300 1000
ns ns
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL are the load resistance and load capacitance of the SO output lines.
40
PD75P0076
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V, 1.8 V AVREF VDD)
Parameter Resolution Absolute accuracy
Note 1
Symbol
Test conditions
MIN. 8
TYP. 8
MAX. 8 1.5 3 3 168/fX 44/fX
Unit bit LSB LSB LSB
VDD = AVREF
2.7 VDD 1.8 V VDD < 2.7 V
VDD AVREF Conversion timeNote 2 Sampling time
Note 3
tCONV tSAMP VIAN RAN IREF AVSS 1000 0.25
s s
V M
Analog input voltage Analog input impedance AVREF current
AVREF
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (1/2 LSB). 2. Time after execution of conversion start instruction until completion of conversion (EOC = 1) (40.1 s: in fX = 4.19 MHz operation) 3. Time after conversion start instruction until completion of sampling (10.5 s: in fX = 4.19 MHz operation)
41
PD75P0076
AC Timing Test Point (Excluding X1, XT1 Input)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock Timing
1/fX tXL tXH
X1 Input
VDD-0.1 V 0.1 V
1/fXT tXTL tXTH
XT1 Input
VDD-0.1 V 0.1 V
TI0, TI1 Timing
1/fTI tTIL tTIH
TI0, TI1
42
PD75P0076
Serial Transfer Timing 3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SI tKSO1, 2
Input Data
SO
Output Data
2-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SB0, 1
tKSO1, 2
43
PD75P0076
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4 KR0 to 3
RESET input timing
tRSL
RESET
44
PD75P0076
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85C)
Parameter Release signal set time Oscillation stabilization wait timeNote 1 Symbol tSREL tWAIT Release by RESET Release by interrupt request Test conditions MIN. 0 215/fX Note 2 TYP. MAX. Unit
s
ms ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 2. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 220/fx 217/fx 215/fx 213/fx fx = at 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.81 ms) (approx. 1.95 ms) Wait time 220/fx 217/fx 215/fx 213/fx fx = at 6.0 MHz (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms)
45
PD75P0076
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution RESET
VDDDR
tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR
tSREL
tWAIT
46
PD75P0076
DC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Input voltage high Symbol VIH1 VIH2 Input voltage low VIL1 VIL2 Input leakage current Output voltage high Output voltage low VDD power supply current VPP power supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Test conditions Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Avoid exceeding +13.5 V for VPP including the overshoot. 2. VDD must be applied before VPP, and cut after VPP. AC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time
Note 2
Symbol (to MD0) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR
Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - -
Test conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
MD1 setup time (to MD0) Data setup time (to MD0) Address hold time
Note 2
(from MD0)
Data hold time (from MD0) MD0data output float delay time VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) MD0data output delay time MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-/low-level width X1 input frequency Initial mode set time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Address Address
Note 2 Note 2
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 During program memory read During program memory read During program memory read During program memory read During program memory read 0 2 2 2 2 130
MHz
s s s s s
ns
data output delay time data output hold time
MD3 hold time (from MD0) MD3data output float delay time
s s
Notes1. Corresponding symbol of PD27C256A 2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not connected to the pin.
47
PD75P0076
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1
D0/P40-D3/P43 D4/P50-D7/P53 tI MD0/P30
Data input tDS tDH
Data output tDV tDF
Data input tDS tDH
tXL
Data input tAS
tAH
tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM1S tM1H
tM1R
tM0S
tOPW
tM3H
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1 tXL D0/P40-D3/P43 D4/P50-D7/P53 tDV tI MD0/P30 tM3HR tDAD tHAD Data output Data output tDFR
MD1/P31
tPCR MD2/P32 tM3SR MD3/P33
48
PD75P0076
10. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator) 10 (TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode + 32-kHz oscillation
0.5
Supply Current IDD (mA)
0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
XT2 330 k 33 pF
Crystal resonator 6.0 MHz
Crystal resonator 32.768 kHz
22 pF
22 pF
33 pF
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
6
7
8
49
PD75P0076
IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator) 10 (TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000 Main system clock HALT mode + 32-kHz oscillation 0.5
Supply Current IDD (mA)
0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main sysyem clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
XT2
Crystal resonator
4.19 MHz 22 pF 22 pF
32.768 kHz 330 k 33 pF 33 pF
Crystal resonator
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
6
7
8
50
PD75P0076
11. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42 22
1 A
21
K L I G J H
F C D N
M
B M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1
51
PD75P0076
42 PIN PLASTIC SHRINK SOP (375 mil)
42
22 detail of lead end
1
A
21 H I
G
3 +7 -3
J
F
E
C D M
M
N
B
K
L S42GT-80-375B-1
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N
MILLIMETERS 18.16 MAX. 1.13 MAX. 0.8 (T.P.) 0.35 +0.10 -0.05 0.125 0.075 2.9 MAX. 2.5 0.2 10.3 0.3 7.15 0.2 1.6 0.2 0.15 +0.10 -0.05 0.8 0.2 0.10 0.10
INCHES 0.715 MAX. 0.044 MAX. 0.031 (T.P.) 0.014 +0.004 -0.003 0.005 0.003 0.115 MAX. 0.098+0.009 -0.008 0.406+0.012 -0.013 0.281+0.009 -0.008 0.063 0.008 0.006 +0.004 -0.002 0.031 +0.009 -0.008 0.004 0.004
52
PD75P0076
12. RECOMMENDED SOLDERING CONDITIONS
The PD75P0076 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Sales representative. Table 12-1. Surface Mounting Type Soldering Conditions
PD75P0076GT: 42-pin plastic shrink SOP (375 mil, 0.8 mm pitch)
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds or less (at 210C or higher), Number of reflow processes: Twice or less Package peak temperature: 215C, Time: 40 seconds or less (at 200C or higher), Number of reflow processes: Twice or less
Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
Solder temperature: 260C or below, Time: 10 seconds or less, Number of flow process: 1, Preheating temperature: 120C or below (Package surface temperature) Pin temperature: 300C or below, Time : 3 seconds or less (per device side)
WS60-00-1
Partial heating
--
Caution
Use of more than one soldering method should be avoided (except for partial heating). Table 12-2. Insertion Type Soldering Conditions
PD75P0076CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
Soldering Method Wave soldering (pins only) Partial heating Soldering Conditions Solder bath temperature: 260 C or less, Time: 10 seconds or less Pin temperature: 300 C or below, Time: 3 seconds or less (per device side)
Caution
Ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly.
53
PD75P0076
APPENDIX A DIFFERENCES AMONG PD75068, 750068 AND 75P0076
PD75068
Mask ROM 0000H to 1F7FH (8064 x 8 bits) 000H to 1FFH (512 x 4 bits) 75X Standard CPU 4 bits x 8 or 8 bits x 4 0.95, 1.91, 15.3 s (during 4.19-MHz operation) 75XL CPU (4 bits x 8 or 8 bits x 4) x 4 banks * 0.67, 1.33, 2.67, 10.7 s (during 6.0-MHz operation) * 0.95, 1.91, 3.81, 15.3 s (during 4.19-MHz operation)
Parameter Program memory
PD750068
Mask ROM 0000H to 1FFFH (8192 x 8 bits)
PD75P0076
One-time PROM 0000H to 3FFFH (16384 x 8 bits)
Data memory
CPU General-purpose register Instruction execution time When main system clock is selected When subsystem clock is selected I/O port CMOS input CMOS input/output N-ch open-drain input/output
122 s (during 32.768-kHz operation)
12 (Connections of on-chip pull-up resistor specified by software: 7) 12 (Connections of on-chip pull-up resistor specified by software) 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 10 V 32 3 * * * channels 8-bit timer/event counter 8-bit basic interval timer Watch timer 4 channels * 8-bit timer/event counter 0 (watch timer output added) * 8-bit timer/event counter 1 (can be used as a 16-bit timer/ event counter) * 8-bit basic interval timer/watchdog timer * Watch timer * 8-bit resolution x 8 channels (successive approximation) * Can operate at the voltage from VDD = 1.8 V 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 13 V 8 (no mask option) Withstand voltage is 13 V
Total Timer
A/D converter
* 8-bit resolution x 8 channels (successive approximation) * Can operate at the voltage from VDD = 2.7 V , 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation)
Clock output (PCL)
* , 1.05 MHz, 262 kHz, 65.5 kHz (Main system clock: during 4.19-MHz operation) * , 1.5 MHz, 375 kHz, 93.8 kHz (Main system clock: during 6.0-MHz operation) * 2, 4, 32 kHz (Main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: during 6.0-MHz operation) 2 modes supported * 3-wire serial I/O mode...MSB/LSB first selectable * 2-wire serial I/O mode
Buzzer output (BUZ)
2, 4, 32 kHz (Main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) 3 modes supported * 3-wire serial I/O mode ...MSB/LSB first selectable * 2-wire serial I/O mode * SBI mode 3 external, 3 internal 1 external, 1 internal VDD = 2.7 to 6.0 V TA = -40 to +85 C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm)
Serial interface
Vectored interrupt Test inputs Power supply voltage Operating ambient temperature Package
3 external, 4 internal
VDD = 1.8 to 5.5 V
* 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) * 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Note Under development
54
PD75P0076
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD75P0076. In the 75XL series, the common relocatable assembler of the series is used together with device files according to the product.
RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS
TM
Order code (Part No.) Supply Medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
Ver.3.30 to Ver.6.2Note IBM PC/ATTM or compatible Refer to OS for IBM PCs
Device file
Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to OS for IBM PCs Supply Medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC
Order code (Part No.)
S5A13DF750068 S5A10DF750068 S7B13DF750068 S7B10DF750068
Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function. Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above.
PROM Write Tools
Hardware PG-1500 This is a PROM programmer which enables you to program a single-chip microcontroller with on-chip PROM by stand-alone or host machine operation by connecting an attached board and a programmer adapter (sold separately). In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed. This is a PROM programmer adapter dedicated for the PD75P0076CU and 75P0076GT. It can be used when connected to a PG-1500. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD 3.5" 2HD 5" 2HC Order code (Part No.)
PA-75P0076CU Software PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
55
PD75P0076
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P0076. Various system configurations using these in-circuit emulators are listed below.
Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the PD750068 subseries, the IE-75000-R is used with a separately sold emulation board (IE75300-R-EM) and emulation probe. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. This is an emulation board for evaluating application systems that use the PD750068 subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator. This is an emulation probe for the PD75P0076CU. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. This is an emulation probe for the PD75P0076GT. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a flexible board (EV-9500GT-42) to facilitate connections with target systems. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 2 IBM PC/AT or compatible Refer to OS for IBM PCs Supply Medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC Order code (Part No.)
IE-75001-R
IE-75300-R-EM EP-750068CU-R EP-750068GT-R EV-9500GT-42 Software IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. This is a service part provided for maintenance purpose only. 2. Ver. 5.00 or later include a task swapping function, but this software is not able to use that function. Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The generic name for the PD750064, 750066, 750068, and 75P0076 is the PD750068 subseries.
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OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS PC DOS
TM
Version Ver.5.02 to Ver.6.3 J6.1/VNote to J6.3/VNote
MS-DOS
Ver.5.0 to Ver.6.22 5.0/VNote to 6.2/VNote
IBM DOSTM
J5.02/VNote
Note Only the English mode is supported. Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
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PD75P0076
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents related to device
Document No. Document Name English Japanese U10165J U10232J U10670J IEM-5606 U10453J
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet PD75P0076 Data Sheet PD750068 User's Manual PD750068 Instruction Table
75XL Series Selection Guide
U10165E
Note
This document U10670E -- U10453E
Note Preliminary product information
Documents related to development tool
Document No. Document Name English Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-750068GT-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual PC-9800 Series (MS-DOS) base IBM PC Series (PC DOS) base EEU-1416 U11345E U10950E EEU-1335 EEU-1346 EEU-1363 EEU-1291 Japanese EEU-846 U11354J U10950J EEU-651 EEU-731 EEU-730 EEU-704
U10540E
EEU-5008
Other related documents
Document No. Document Name English IC Package Manual Semiconductor Device Mounting Technology Manual NEC Semiconductor Device Quality Grades NEC Semiconductor Device Reliability and Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcontroller-related Product Guide --Third Party Products-- C10943X C10535E C11531E C10983E -- MEI-1202 -- C10535J C11531J C10983J MEM-539 MEI-603 U11416J Japanese
Caution The contents of the documents listed above are subject to change without prior notice to users. Make sure to use the latest edition when starting design.
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PD75P0076
[MEMO]
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PD75P0076
NOTES FOR CMOS DEVICES
(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD75P0076
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD75P0076
MS-DOS is a trademark of Microsoft Corporation. PC DOS, PC/AT, and IBM DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
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